1. Field of the Invention
The present invention generally relates to a thin film transistor liquid crystal display, and more particularly to a thin film transistor liquid crystal display capable of fast driving and having enhanced display quality.
2. Description of the Related Art
The thin film transistor liquid crystal display (hereinafter "TFT-LCD") has advantages of excellent response characteristics and is appropriate for high number of pixels, so that the TFT-LCD is able to realize high display quality and large size of display devices comparable with the cathode ray tube (CRT).
The TFT-LCD comprises a TFT array substrate in which a thin film transistor and a pixel electrode are formed, a color filter substrate in which a color filter and a counter electrode are formed, and a liquid crystal layer sandwiched between the TFT array substrate and the color filter substrate.
In the TFT-LCD, it is required to obtain excellent display quality that a first signal applied from data line should be uniformly maintained until a second signal is applied. So as to uniformly maintain the applied signal, a storage electrode for obtaining a storage capacitance C.sub.st is provided at each pixel. The storage electrode is provided in the form of a line separated from a gate line, or in another form protruding from the gate line. The former type is called as "storage on common" and the later "storage on gate".
FIG. 1 is a plane view for showing a TFT array substrate provided with a conventional storage electrode of the storage on gate type. As shown in the drawing, a plurality of gate lines 1 are arranged in rows and a plurality of data bus lines 4 are arranged perpendicular to the gate lines 1. A storage electrode 2 is provided in the form protruding from the gate line 1 within the pixel area defined by a pair of gate lines 1 and a pair of data lines 4. A pixel electrode 6 made of a transparent metal layer, for example an ITO metal layer, is disposed to be overlapped with the storage electrode 2 within the pixel area.
A TFT 10 is formed at a portion of intersection of the gate line 1 and the data line 4. The TFT 10 includes a gate electrode, i.e. a part of the gate line 1, a source electrode 7 and a drain electrode 8 disposed to be overlapped with the gate electrode. The drain electrode 8 has a form withdrawn from the data line 4, and the source electrode 7 is disposed to be opposed with the drain electrode 8 and in contact with the pixel electrode 6.
However, it is very difficult to utilize the fast operation in the TFT-LCD having the above-described TFT array substrate since there is occurred RC-Delay due to a storage capacitance C.sub.st, a parasitic capacitance C.sub.gs between a part of the gate line i.e. the gate electrode and the source electrode, and a parasitic capacitance C.sub.gd between the gate electrode and the drain electrode defined as following equation 1. EQU .tau.=R.multidot.C.sub.total =R.multidot.(.SIGMA.C.sub.gs +.SIGMA.C.sub.gd.SIGMA.C.sub.st) equation 1
Herein, .tau. means a degree of signal delay and R means resistance value of the gate line.
Further, the TFT array substrate as constituted above is formed conventionally by a divisional exposure process. However, as shown in FIGS. 2a and 2b, the overlapping rate of a part of the gate line 1, i.e. the gate electrode and the source electrode 7, and the overlapping rate of the gate electrode and the drain electrode 8 are changed due to a misalign of an exposing mask, thereby occurring changes in the value of parasitic capacitance. Therefore, as shown in following equation 2, display quality is degraded due to the difference of brightness between the respective divisional exposure regions.
{character pullout}V.sub.p =C.sub.gs /C.sub.gs +C.sub.lc +C.sub.st X {character pullout}V.sub.g equation 2
Herein, {character pullout}V.sub.p means the variation of pixel voltage, i.e. the kick-back voltage, C.sub.gs means a parasitic capacitance between the gate electrode and the source electrode, C.sub.lc means a parasitic capacitance of liquid crystal, and {character pullout}V.sub.g means the variation of gate voltage.